1. Field of Invention
Embodiments of the present invention relate to a semiconductor device and, more particularly, to a non-volatile memory device having memory cells stacked in three dimensions.
2. Description of Related Art
A non-volatile memory device retains data even in the absence of power supply. Two-dimensional memory devices in which memory cells are fabricated in a single layer over a silicon substrate have reached physical limits in increasing their degree of integration. Accordingly, three-dimensional non-volatile memory devices in which memory cells are stacked in a vertical direction over a silicon substrate have been proposed.
The structure and features of a conventional three-dimensional (3-D) memory device are described below with reference to the accompanying drawings.
FIG. 1 is a perspective view illustrating the structure of a conventional 3-D non-volatile memory device. In FIG. 1, interlayer insulating layers are not depicted for illustration purposes.
As shown in FIG. 1, a conventional non-volatile memory device may include U-shaped channel layers CH that are arranged in a first direction I-I′ and a second direction II-II′crossing the first direction I-I′. Here, each of the U-shaped channel layers CH may include a pipe channel layer P_CH and a pair of a source side channel layer S_CH and a drain side channel layer D_CH. The pipe channel layer P_CH may be formed in a pipe gate PG. The source side channel layer S_CH and the drain side channel layer D_CH may be coupled to the pipe channel layer P_CH.
In addition, the memory device may include source side word line layers S_WL stacked over the pipe gate PG along the source side channel layer S_CH and drain side word line layers D_WL stacked over the pipe gate PG along the drain side channel layer D_CH. Here, a source selection line layer SSL may be stacked on top of the source side word line layers S_WL, and a drain selection line layer DSL may be stacked on top of the drain side word line layers D_WL.
According to the above-described structure of the memory device, memory cells MC may be stacked along the U-shaped channel layer CH. A drain selection transistor DST and a source selection transistor SST may be formed at both ends of the U-shaped channel layer CH. Therefore, strings having a U shape may be arranged.
In addition, the memory device may include bit line layers BL and a source line layer SL. The bit line layers BL may be coupled to the drain side channel layers D_CH and extend in the first direction I-I′. The source line layer SL may be coupled to the source side channel layer S_CH and extend in the second direction II-II′.
The conventional 3-D non-volatile memory device may be configured to perform a program operation and a read operation by separately controlling voltages of the source selection line layer SSL and the drain selection line layer DSL of each string, which may make a operating method thereof complicated. In addition, since a stacked structure of the word line layers and the selection line layers has a great height to increase storage capacities of the memory device, the stacked structure may lean.